The present invention relates to an integrated circuit comprising, inter alia, a resynchronization module having a clock input for a clock signal, a signal input for input data signal, and an output, which module includes a D-type flip-flop having its signal input coupled to the signal input of the module and having its clock input coupled to the clock input of the module.
It also relates to a liquid crystal display device.
The invention applies to those cases which require two signals having frequencies of which one is a multiple of the other and whose transitions are perfectly in phase. It applies, inter alia, to an interface for liquid crystal displays, for deriving the pixel frequency from the line clock frequency.
A synchronization module can be formed by a simple D-type flip-flop. A more sophisticated arrangement including a D flip-flop, whose signal input and clock input form the corresponding inputs of the arrangement, is described in the document EP 0 716 501. Starting from an input signal and a clock signal, this arrangement supplies a first and a second indication of the detection of a signal transition, these two indications being identical when the clock is in phase with the signal.